Integrated circuits can include line driver circuits that can drive signals across relatively long conductive lines. For example, memory circuits can include word lines, each connected to a row of memory cells that can be driven between select and de-select states. Higher density memory circuits can partition word lines to reduce overall word line size, and thus drive such word lines faster. In such architectures, word lines can include global word lines (GWLs) each of which can activate a number of sub word lines (SWLs).
Conventional SWL drivers can suffer from gate induced drain leakage (GIDL) when implemented in sub micron technologies. Such SWL gate induced drain leakage can be as much as 8 to 10% of the chip standby current (ISB).
To better understand various features of the disclosed embodiments, a conventional SWL driver will now be described with reference to FIG. 7. FIG. 7 shows a conventional SWL driver 700 that includes a PMOS device P70, and n-channel MOS (NMOS) devices N70 and N72. Device P70 has a source that receives a block select signal BLK, a drain connected to SWL 702, and a gate connected to a global word line select signal GWLB. Device N70 has a source connected to a low power supply GND, a drain connected to SWL 702, and a gate also connected to signal GWLB. Device N72 can have a drain connected to SWL 702, a source connected to low power supply GND, and a gate connected to receive a signal BLKB that is the inverse of signal BLK.
Conventional SWL driver 700 can be placed in a standby mode by driving signal BLK low, signal BLKB high, while signal GWLB can be high. In such a state, significant current leakage (shown by arrows “IIk”) can occur through an n-well containing device P70, because a source and drain of device P70 can be at a ground potential, while the gate of the device is at a higher potential. Such leakage has GIDL as the dominant component if |Vgd| or |Vgs|=Vpwr (magnitude of gate-to-drain or gate-to-source voltage is higher or equals to supply voltage Vpwr) for any OFF transistor in standby mode. Gate induced drain leakage is not a function of gate length, and can vary exponentially with |Vgd| or |Vgs| for an off transistor.
A first conventional approach to addressing GIDL can be to reduce a gate potential applied at the affected device (e.g., PMOS P70). However, such an approach can require additional power control and regulation circuitry, and thus increases die (i.e., integrated circuit) area and design complexity. A second conventional solution can be to reduce the number of SWL drivers by increasing the number of memory cells driven by a given SWL. This can have the disadvantage of reduced speed due to increased loading. A third conventional solution can be to reduce the potential at the n-well containing the affected PMOS device, to some constant lower voltage or to ground (zero volts). Disadvantages of such an approach can also be an additional regulator circuit, resulting in increased die area and design complexity. Still further, driving an n-well to a zero volt potential can cause an increase in standby currents as a parasitic npn transistor can be formed with nearby n-wells.